rh1056a 1 precision, high speed, jfet input operational ampli er the rh1056a jfet input operational ampli? ers combine precision speci? cations with high speed performance. for the ? rst time, 16v/s slew rate and 6.5mhz gain- bandwidth product are simultaneously achieved with offset voltage of typically 50v, 1.2v/c drift, bias currents of 40pa at 70c. the wafer lots are processed to ltcs in-house class s ? ow to yield circuits usable in stringent military applications. supply voltage ........................................................20v differential input voltage.........................................40v input voltage ...........................................................20v output short-circuit duration .......................... inde? nite operating temperature range................ C55c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) burn-in circuit description absolute maximum ratings top view h package 8-lead to-5 metal can nc bal v + out C in bal +in v C 8 7 6 5 3 2 1 4 + C top view w package 10-lead cerpac 1 5 4 3 2 10 6 7 8 9 nc bal Cin +in v C nc nc v + out bal package information C + 10k 200 10k 20v 7 6 4 rh1056a bi 2 3 C20v
rh1056a 2 symbol param eter conditions notes t a = 25c sub- group C55c t a 125c sub- group units min typ max min typ max v os input offset voltage rh1056amw rh1056amh 2 300 300 4 4 900 1100 2, 3 2, 3 v v i os input offset current fully warmed up t a = 125c 4 4 10 1 1.5 2 pa na i b input bias current fully warmed up t a = 125c 4501 3.0 2 pa na r in input resistance 10 12 a vol large-signal voltage gain v s = 15v, v o = 10v, r l = 2k v s = 15v, v o = 10v, r l = 1k 150 130 4 4 40 5,6 v/mv v/mv v o output voltage swing v s = 15v, r l = 2k 12 4 12 5,6 v v cm input common mode voltage range v s = 15v 11 1 11 2,3 v cmrr common mode rejection ratio v cm = 11v v cm = 10.5v 86 1 85 2,3 db db psrr power supply rejection ratio v s = 10v to 18v v s = 10v to 17v 90 1 88 2,3 db db i s supply current v s = 15v 6.5 1 ma sr slew rate av = 1, v s = 15v 10 7 v/s gbw gain-bandwidth product v s = 15v 6.5 mhz e n input noise voltage density v s = 15v, f = 10hz v s = 15v, f = 1khz 28 14 fa/ hz fa/ hz i n input noise current density v s = 15v, f = 10hz v s = 15v, f = 1khz 1.8 1.8 fa/ hz fa/ hz c in input capacitance 4 4 pf (preirradiation) (note 3) symbol parameter conditions notes 10krad (si) 20krad (si) 50krad (si) 100krad (si) 200krad (si) units min max min max min max min max min max v os input offset voltage 2 300 300 370 570 870 v i os input offset current 4 10 50 150 250 350 pa i b input bias current 4 50 250 500 1000 2000 pa a vol large-signal voltage gain v o = 10v, r l 2k v o = 10v, r l 1k 150 130 150 130 150 130 100 87 75 65 v/mv v/mv v o output voltage swing r l 2k 12 12 12 12 12 v v cm input common mode voltage range v s = 15v 11 11 11 11 11 v cmrr common mode rejection ratio v cm = 11v 86 86 86 86 86 db psrr power supply rejection ratio v s = 10v to 18v 90 90 90 90 90 db i s supply current 7 7 7 7 7 ma sr slew rate a v = 1, v s = 15v 10 10 9 9 9 v/s c in input capacitance 3(typ) 3(typ) 3(typ) 3(typ) 3(typ) pf table 1: electrical characteristics table 1a: electrical characteristics (postirradiation) (note 5)
rh1056a 3 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. total dose bias circuit table 2: electrical test requirements C + 10k 10k 15v 0.1f 0.1f rh1056a bc 6 7 4 2 3 8v C15v mil-std-883 test requirements subgroup final electrical test requirements (method 5004) 1*,2,3,4,5,6, 7 group a test requirements (method 5005) 1,2,3,4,5,6, 7 group b and d for class s, and class c and d for class b** end point electrical parameters (method 5005) 1 *pda applies to subgroup 1. see pda test notes. **for d3, d4, b5 and b6 v os limit as follows w package h package 500v 700v pda test notes the pda is speci? ed as 5% based on failures from group a, subgroup 1, tests after cooldown as the ? nal electrical test in accordance with method 5004 of mil-std-883. the veri? ed failures of group a, subgroup 1, after burn-in divided by the total number of devices submitted for burn-in in that lot shall be used to determine the percent for the lot. linear technology corporation reserves the right to test to tighter limits than those given. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: unless otherwise speci? ed, the absolute maximum negative input voltage is equal to the negative power supply voltage. offset voltage is measured under two different conditions: (a) approximately 0.5 seconds after application of power, (b) at t a = 25c only, with the chip heated to approximately 45c to account for chip temperature rise when the device is fully warmed up. table 1a: electrical characteristics note 3: unless otherwise stated, v s = 15v; and v os , i b and i os are measured at v cm = 0v. note 4: the input bias currents are junction leakage currents which approximately double for every 10c increase in the junction temperature, t j . due to limited production test time, the input bias currents measured are correlated to junction temperature. in normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, p d . t j = t a + ( ja ? p d ) where ja is the thermal resistance from junction to ambient. note 5: unless otherwise stated, v s = 15v, v cm = 0v and t a = 25c.
rh1056a 4 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 1989 lt 0209 rev c ? printed in usa id no. 66-10-0160 rev c 0209 typical performance characteristics input bias current common mode rejection ratio input offset current power supply rejection ratio input offset voltage open-loop gain total dose krads (si) 1 input offset voltage (mv) 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 10 100 1000 1056a g01 v s = 15v v cm = 0v total dose krads (si) 1 open-loop gain (v/mv) 350 300 250 200 150 100 50 0 10 100 1000 1056a g02 v s = 15v v o = 10v r l = 2k r l = 1k total dose krads (si) 1 input bias current (na) 3.0 2.5 2.0 1.5 1.0 0.5 0 C0.5 10 100 1000 1056a g03 v s = 15v v cm = 0v total dose krads (si) 1 common mode rejection ratio (db) 130 120 110 100 90 80 70 60 10 100 1000 1056a g04 v s = 15v v cm = 11v total dose krads (si) 1 input offset current (na) 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 10 100 1000 1056a g05 v s = 15v v cm = 0v total dose krads (si) 1 power supply rejection ratio (db) 130 120 110 100 90 80 70 60 10 100 1000 1056a g06 v s = 10v to 18v
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